1. Field of the Invention
The present invention generally relates to clamping circuits, and more particularly, to a circuit configuration for clamping a voltage generated in a semiconductor device to a constant voltage.
2. Description of the Background Art
Recently, a semiconductor device is configured by using a single power source (a configuration using one kind of power supply voltage in addition to a power supply potential serving as a ground potential in general) in order to facilitate system build-up. On the other hand, in a semiconductor device such as a semiconductor memory, a potential which is different from an external or internal power supply voltage Vcc is often required. In such a case, a potential required in the semiconductor device is generated from the power supply voltage Vcc.
FIG. 9 is a diagram showing a general configuration of a semiconductor memory. In FIG. 9, a configuration of a dynamic random access memory is shown as an example of a semiconductor memory.
In FIG. 9, the semiconductor memory includes a memory cell array 100 having a plurality of dynamic type memory cells arranged in a matrix of rows and columns, an address buffer 102 generating an internal address signal according to an externally applied address signal A0 to An, a row decoder 104 decoding an internal row address signal from address buffer 102 to generate a signal selecting a corresponding row in memory cell array 100, a word driver 106 transmitting a word line driving signal to a corresponding row in memory cell array 100 in response to a row select signal from row decoder 104, a column decoder 110 decoding an internal column address signal from address buffer 102 to generate a signal for selecting a corresponding column in memory cell array 100, a sense amplifier for sensing and amplifying storage data of a memory cell connected to the selected row in memory cell array 100, and an IO gate for connecting a corresponding column in memory cell array 100 to an internal data line in response to a column select signal from column decoder 110. In FIG. 9, the sense amplifier and the IO gate are shown in one block 108.
The semiconductor memory further includes an input/output circuit 112 for carrying out input/output of data to and from the outside of the memory, a clock control circuit 114 for generating various internal control signals in response to externally applied control signals /RAS ("/" before reference characters indicating that a signal is active or asserted at a low level), /CAS and /WE, a VBB generating circuit 116 for applying a predetermined bias voltage VBB to a semiconductor substrate on which the semiconductor memory is formed, and a Vpp generating circuit 118 for generating a boost signal Vpp higher than the power supply voltage Vcc to be transmitted to the selected row of memory cell array 100.
The signal /RAS is a row address strobe signal. The signal /RAS determines a memory cycle of the semiconductor memory, as well as gives a timing at which address buffer 102 takes in the row address signal. The signal /CAS is a column address strobe signal. The signal /CAS gives a timing at which address buffer 102 takes in the column address signal, as well as an operating timing of circuitry associated with column selection of the semiconductor memory. The signal /WE is a write enable signal. The signal /WE determines whether the semiconductor memory is in a data reading mode or a data writing mode. The various internal control signals generated from clock control circuit 114 are applied to various circuit portions. However, in FIG. 9, it is simply shown that they are applied to address buffer 102, row decoder 104, and Vpp generating circuit 118. Operations will now be described briefly.
The semiconductor memory shown in FIG. 9 is a dynamic random access memory. A row address signal and a column address signal are applied to address buffer 102 in a time division multiplexed manner. Address buffer 102 takes in an external address signal in response to an internal control signal generated in response to the signal /RAS from clock control circuit 114 to generate an internal row address signal. Row decoder 104 decodes the internal row address signal to generate a signal selecting a row (a word line) in memory cell array 100.
Vpp generating circuit 118 receives the power supply voltage Vcc (in FIG. 9, Vcc is shown being applied externally) to generate the boost signal Vpp in response to an internal control signal from clock control circuit 114. Word driver 106 transmits the boost signal Vpp applied from Vpp generating circuit 118 onto a row (a word line) in memory cell array 100 designated by a row select signal from row decoder 104. As a result, one row is brought into a selected state in memory cell array 100, and storage data of a memory cell connected to the selected row is transmitted onto a corresponding column (a bit line). Then, the sense amplifier included in block 108 is activated (by a control signal from clock control circuit 114), and storage data of a memory cell transmitted onto each column is amplified.
On the other hand, address buffer 102 generates an internal column address signal from an external address signal in response to an internal control signal generated from clock control circuit 114 in response to the signal /CAS. Column decoder 110 decodes an internal column address signal from address buffer 102 to generate a column select signal. Data of each memory cell has already been sensed and amplified by the sense amplifier in block 108 at the time of generating the column select signal, whereby data on each column has been brought into a stable state.
The IO gate in block 108 is rendered conductive in response to a column select signal from column decoder 110 to connect a corresponding column in memory cell array 100 to input/output circuit 112. Input/output circuit 112 is responsive to a control signal from clock control circuit 114 for generating internal write data from external write data to transmit the resultant data to block 108 in a data writing operation mode, and for generating external read data from internal read data transmitted from the IO gate in block 108 in a data reading operation mode.
As described above, writing or reading of data is carried out for a memory cell arranged corresponding to a crossing of a row and a column selected by row decoder 104 and column decoder 110. Description will now be given on functions of the boost signal Vpp transmitted onto the selected row in memory cell array 100.
FIG. 10 is a diagram showing a configuration of a dynamic type memory cell. In FIG. 10, a dynamic type memory cell 120 includes a memory cell capacitor 124 for storing information in the form of electric charges, and a transfer gate 122 responsive to a signal potential on a word line WL for connecting memory cell capacitor 124 to a corresponding bit line (a bit line BL in FIG. 10). Memory cell capacitor 124 has one electrode (a cell plate) connected to a predetermined reference potential Vcp. The word line WL corresponds to a row of memory cell array 100 shown in FIG. 9, and bit lines BL and /BL correspond to a column of memory cell array 100 shown in FIG. 9. Bit lines BL and /BL constitute a pair, and memory cell 120 is disposed at a crossing of one word line and a pair of bit lines BL, /BL. In FIG. 10, the state is shown where memory cell 120 is disposed at a crossing of the word line WL and the bit line BL. Ordinarily, another dynamic type memory cell is disposed at a crossing of an adjacent word line and the bit line /BL. Sensing operation of data of the dynamic type memory cell shown in FIG. 10 will now be described with reference to an operating waveform diagram shown in FIG. 11.
When the word line WL is selected, the boost signal Vpp is transmitted onto the word line WL from word driver 106 shown in FIG. 9. As a result, transfer gate 122 in memory cell 120 is rendered conductive, and memory cell capacitor 124 is coupled to the bit line BL. The bit lines BL and /BL are precharged to an intermediate potential (Vcc/2) at the time of stand-by, and brought into an electrically floating state before the potential of the word line rises. This causes electric charges to move between the bit line BL and memory cell capacitor 124, and the potential of the bit line BL changes according to storage data of memory cell capacitor 124. In the state shown in FIG. 11, memory cell 120 stores data "0", and the potential of the bit line BL decreases. The other bit line /BL does not have the selected memory cell connected thereto, and therefore holds the precharge potential Vcc/2.
Then, the sense amplifier is activated to differentially amplify the potential difference between the bit lines BL and /BL. After writing or reading of data to and from memory cell 120 is carried out, one memory cycle is completed, and the potential of the word line WL falls to an "L" level.
Transfer gate 122 in dynamic type memory cell 120 is ordinarily constituted of an n channel MOS transistor (an insulating gate type field effect transistor), as shown in FIG. 10. Therefore, transfer gate 122 can pass a voltage of the potential applied to its gate less its own threshold voltage. If the potential of the word line WL is at a level of the power supply voltage Vcc, a voltage Vcc-Vth is transmitted to memory cell capacitor 124. Vth is a threshold voltage of transfer gate 122.
As memory capacity of the semiconductor memory increases, the size of the memory cell decreases. When C represents a capacitance and V represents a transmitted potential, an amount of storage electric charges Q is expressed as follows: EQU Q=C.multidot.(V-Vcp)
As shown in the above equation, in order to store sufficient electric charges in the memory cell capacitor, it is necessary to make the transmitted voltage V as large as possible. Therefore, the potential of the word line WL is boosted above the power supply voltage Vcc in order to transmit the power supply voltage Vcc to memory cell capacitor 124. By transmitting the boost signal Vpp at the time of rising of the potential of the word line WL, the rising rate of the potential of the word line WL is increased, and storage data of memory cell 120 is transmitted onto the bit line BL at a high speed.
Such boost voltage Vpp is generated on-chip from the power supply voltage Vcc by using a boosting circuit using a capacitive coupling by bootstrap capacitance, a boosting circuit using a charge pump operation, or the like.
FIG. 12 is a diagram showing functions of a substrate bias voltage generated from the VBB generating circuit shown in FIG. 9. In FIG. 12, a cross-sectional structure of one MOS transistor is shown. In FIG. 12, the MOS transistor includes N type impurity regions 142 and 144 of high impurity concentration formed on the surface of a P type semiconductor substrate (or a P well), and a gate electrode 146 formed on the substrate surface between impurity regions 142 and 144 with a gate insulating film 145 interposed therebetween.
The MOS transistor shown in FIG. 12 is an n channel type transistor. When a voltage of an "H" level is applied to gate electrode 146, an inversion layer is formed in a channel region 147 under gate electrode 146, and impurity regions 142 and 144 are connected through the inversion layer of low resistance in the surface of channel region 147. As a result, the MOS transistor is brought into an on state. A threshold voltage Vth of such an MOS transistor changes depending on a surface impurity concentration of channel region 147. The surface impurity concentration is varied depending on various parameters of the manufacturing process.
In order to suppress variation of the threshold voltage caused by such variation of the impurity concentration, a constant bias potential VBB is applied to semiconductor substrate 140. Ordinarily, a negative voltage of -2 to -3 V is applied to P type semiconductor substrate 140 in order to stabilize the threshold voltage of the MOS transistor. By applying the bias voltage VBB, junction capacitance formed between impurity regions 142 or 144 and semiconductor substrate 140 decreases, thereby improving an operating speed of the MOS transistor.
The MOS transistor is electrically isolated from the adjacent cell by a cell isolating region (a cell isolating oxide film) 148. A signal line 150 is disposed on cell isolating region 148. In this configuration, an inversion layer is formed under cell isolating region 148 by a voltage applied to the signal line or interconnection layer 150. The bias voltage VBB serves to prevent a parasitic MOS transistor from being rendered conductive.
Such substrate bias voltage VBB is also generated on-chip in the semiconductor memory by using a circuit such as a charge pump circuit (using a capacitor) from the power supply voltage Vcc.
A voltage signal generated on-chip in the semiconductor memory includes a sense amplifier connection control signal in a shared sense amplifier configuration in addition to the word line boost signal and the substrate bias voltage as described above.
FIG. 13 is a diagram showing an arrangement of the shared sense amplifier in the semiconductor memory. In FIG. 13, a sense amplifier 160 is shared by a bit line pair BLA, /BLA of a memory block MBA and a bit line pair BLB, /BLB of a memory block MBB. The bit line pair BLA, /BLA of the memory block MBA and sense amplifier 160 are connected through a connection gate 162, and sense amplifier 160 and the bit line pair BLB, /BLB of the memory block MBB are connected through a connection gate 164. Description will now be given on sensing operation of memory cell data using the shared sense amplifier shown in FIG. 13 with reference to its operating waveform diagram shown in FIG. 14.
When the signal /RAS falls, one memory cycle starts. In response to falling of the signal /RAS, a decoding operation of the row address signal and a word line selecting operation are carried out. In parallel with these operations, only the memory block including a selected word line is connected to sense amplifier 160, and the other memory block is disconnected from sense amplifier 160. In the state before this, sense amplifier 160 is connected to bit line pairs BLA, /BLA, and BLB, /BLB. Control of connection/disconnection between sense amplifier 160, and the bit line pairs BLA, /BLA and BLB, /BLB is carried out by control signals .phi.A and .phi.B, respectively.
Various methods are considered as manners of generating the control signals .phi.A and .phi.B. As shown in FIG. 14 (i), at the time of stand-by, both the control signals .phi.A and .phi.B maintain the boost signal Vpp level, and the control signal .phi.A or .phi.B for a non-selected memory block (a memory block not including a selected word line) falls to the ground potential Vss level. As a result, only a bit line pair of one memory block is connected to sense amplifier 160.
In place of the above configuration, as shown in FIG. 14 (ii), both the control signals .phi.A and .phi.B are at the power supply voltage Vcc level at the time of stand-by, the control signal for the selected memory block attains the boost signal Vpp level, and the control signal for the non-selected memory block attains the ground potential Vss level. In any methods, as for the selected memory block, the connection gate is rendered conductive by the control signal of the boost signal Vpp level, thereby connecting the bit line pair and sense amplifier 160.
After connection of the selected memory cell block and sense amplifier 160 and disconnection of the non-selected memory cell block and sense amplifier 160, the sense amplifier activation signal .phi.SA is activated, and sense amplifier 160 carries out a sensing operation. As a result, data of the memory cell connected to the selected word line is sensed and amplified.
As described above, by applying the signals .phi.A and .phi.B of the boost signal Vpp level to connections gate 162 or 164 at the time of sensing operation, transmission loss of a signal in connection gate 162 or 164 (caused by the threshold voltage of the MOS transistor constituting the connection gate) is eliminated, the signal of the power supply voltage Vcc level is reliably transmitted onto a bit line.
In the shared sense amplifier configuration as described above, the memory cell array block is divided into two. Therefore, the length of a bit line in each memory cell array is shortened, and bit line capacitance can be made small, whereby it is possible to transmit a sufficient read out voltage onto a bit line at a high speed.
FIG. 15 is a diagram showing schematically a configuration for generating each control signal in the shared sense amplifier arrangement shown in FIG. 13. In FIG. 15, circuitry for generating shared sense control signals includes a RAS buffer 170 receiving the external signal /RAS for generating the internal RAS signal, a sense amplifier activating circuit 172 receiving the internal RAS signal from RAS buffer 170 for generating the sense amplifier activation signal .phi.SA at a predetermined timing, a Vpp generating circuit 176 generating the boost signal Vpp at a predetermined timing in response to the internal RAS signal from RAS buffer 170, and a disconnection control circuit 174 generating the disconnection control signals .phi.A and .phi.B in response to the internal RAS signal, the internal address signal RA, and the boost signal Vpp. As the internal address signal RA, for example, a higher bit of the internal row address signal is used. It is possible to identify a memory block including a selected word line by a predetermined number of higher bits of the row address signal RA. Vpp generating circuit 176 generates the boost signal Vpp on-chip from the power supply voltage Vcc.
As described above, in the semiconductor memory, signals of various voltage levels are generated on-chip from the power supply voltage Vcc. Not only in the dynamic random access memory but also in EEPROM such as a flash memory (an electrically programmable and erasable semiconductor memory device), a program voltage required at the time of programming operation is generated on-chip from the power supply voltage Vcc.
When the boost signal Vpp and the substrate bias voltage VBB are generated on-chip from the power supply voltage Vcc, in order to ensure an operating margin, a voltage of a predetermined level or more (or in the case of a negative voltage, a voltage of a predetermined level or less) is required.
On the other hand, as a semiconductor device such as a semiconductor memory is made high in density, the size of components is more and more miniaturized. Therefore, from the standpoint of breakdown voltage of the components, it is necessary to prevent application of a higher voltage than required. For example, when the boost signal Vpp is applied as a word line drive signal, if a higher voltage than required is applied to a word line, word line destruction (open-circuit of a word line, dielectric breakdown of an interlayer insulating film) or the like occurs.
Also in the case of the substrate bias voltage VBB of a negative voltage, when a PN junction is in a reverse-biased state and a negative potential of the substrate bias voltage VBB is decreased more than required, it is considered that the reverse-biased state of the PN junction is further enhanced, causing destruction of the PN junction (the case where a signal of an "H" level is applied to an N region).
In order to prevent generation of a voltage of a level higher than required, a clamping circuit is generally provided as shown in FIG. 16. In FIG. 16, a configuration in which a voltage level of the boost signal Vpp generated by a Vpp generating circuit 180 is clamped at a certain level, is shown as an example. A configuration of a circuit generating the substrate bias voltage VBB is similar thereto. A clamping circuit 182 serves to prevent a level of the boost signal Vpp generated from Vpp generating circuit 180 from exceeding a predetermined voltage level.
FIG. 17 is a diagram showing a specific configuration of the clamping circuit shown in FIG. 16. In FIG. 17, the clamping circuit includes MOS transistors 8a to 8n connected in series between a node 200 and a node supplying a ground potential (GND) serving as a reference potential. Each of the MOS transistors 8a to 8n is diode-connected to cause voltage drop of its own threshold voltage Vth. Node 200 is coupled to a signal line to which the boost signal Vpp is transmitted. Operations of the clamping circuit shown in FIG. 17 will now be described with reference to a voltage-current characteristic shown in FIG. 18. In FIG. 18, the ordinate shows a current I and the abscissa shows a voltage V. A curve a shows a voltage-current characteristic of one MOS transistor, and a curve b shows a voltage-current characteristic in the clamping circuit shown in FIG. 17.
Each of the MOS transistors 8a to 8n has its gate terminal and drain terminal connected, and operates in a saturation region. The voltage-current characteristic of the MOS transistor in the saturation region is given by the curve a shown in FIG. 18. More specifically, when a current Ids flows through one MOS transistor, the voltage-current characteristic is given by the following equation: EQU Ids=.beta.(Vgs-Vth).sup.2
In the equation, Ids represents a drain current, Vgs represents a voltage between gate and source, and Vth represents a threshold voltage. A coefficient .beta. is a constant determined by geometrical configuration and the like of the MOS transistor. The voltage-current characteristic of one MOS transistor is a square characteristic.
When the number of MOS transistors 8a to 8n used in the clamping circuit shown in FIG. 17 is N, the current I flowing from node 200 to the ground potential (reference potential supply node) GND is given by the following equation, providing that the threshold voltages Vth of respective MOS transistors 8a to 8n are all equal: ##EQU1## It is possible to provide the above equation on condition that on-resistances of the MOS transistors 8a to 8n are equal, voltages between drain and source applied to respective MOS transistors 8a to 8n are the same, and that values of current flowing through respective MOS transistors 8a to 8n are the same.
In the above-described equation, when the voltage V at node 200 satisfies the relation V&gt;N.multidot.Vth, the current I flows. More specifically, in a conventional clamping circuit, N times of the threshold voltage Vth of each of the MOS transistors 8a to 8n, which are components, is taken as a reference voltage. When the voltage V at node 200 exceeds the value N.multidot.Vth, a current flows from node 200 to the ground potential GND, causing the potential at node 200 to decrease. As a result, unnecessary increase of the voltage V at node 200 is prevented.
However, as described above, when the MOS transistors are connected just in series, a voltage applied across to one MOS transistor is V/N. Therefore, as seen in the above equation, the voltage-current characteristic of the clamping circuit provides a curve more gentle than that of a single MOS transistor, as shown by the curve b of FIG. 18. More specifically, in the clamping circuit shown in FIG. 17, an amount of change of the current I with respect to change of the voltage V at node 200 is 1/N.sup.2 of that of the single MOS transistor, whereby it is not possible to make a rapid current flow according to the change of the voltage V at node 200. Therefore, it is not possible to respond to the change of the voltage V at node 200 at a high speed, causing problems that an amount of current at the time of clamping operation is insufficient, and that a leak current flows when not required.
Since the clamping potential is determined by an integer multiple of the threshold voltage Vth of the MOS transistor, only discrete values can be implemented as clamping potentials, causing a problem that an arbitrary clamping potential cannot be set easily.
As the number of MOS transistors included in the clamping circuit increases, the MOS transistor distant from the ground potential GND is more affected by a substrate effect, thus having larger threshold voltage Vth. More specifically, when the substrate potential is constant in respective MOS transistors 8a to 8n, the source potential increases as the MOS transistor becomes distant from the ground potential GND, causing the difference between the source potential and the substrate potential to increase. As a result, the substrate bias voltage increases effectively, and the threshold voltage of the MOS transistor increases. Therefore, another problem occurs that it is difficult to subtly adjust the clamping potential.